Did you forget an if statement somewhere? Did you remember to give every possible case statement assignment? These are the types of errors that are very easy to make when you do not simulate your design. A great simulation will exercise all possible states of the design to ensure that all input scenarios will be handled appropriately. Simulation allows the designer to stimulate his or her design and see how the code that they wrote reacts to the stimulus. Simulation is a critical step of designing FPGAs and ASICs. This tutorial explains first why simulation is important, then shows how you can acquire Modelsim Student Edition for free for your personal use. It is the most widely use simulation program in business and education. Modelsim is a program created by Mentor Graphics used for simulating your VHDL and Verilog designs. Tutorial - Using Modelsim for Simulation, for Beginners.
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